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NTD4804N Power MOSFET
Features
30 V, 117 A, Single N-Channel, DPAK/IPAK
* * * *
Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb-Free Devices
V(BR)DSS 30 V
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RDS(on) MAX 4.0 m @ 10 V 5.5 m @ 4.5 V D ID MAX 117 A
Applications
* CPU Power Delivery * DC--DC Converters * Low Side Switching
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter Drain--to--Source Voltage Gate--to--Source Voltage Continuous Drain Current (RJA) (Note 1) Power Dissipation (RJA) (Note 1) Continuous Drain Current (RJA) (Note 2) Power Dissipation (RJA) (Note 2) Continuous Drain Current (RJC) (Note 1) Power Dissipation (RJC) (Note 1) Pulsed Drain Current tp=10ms Current Limited by Package TA = 25C TA = 85C TA = 25C TA = 25C Steady State TA = 85C TA = 25C TC = 25C TC = 85C TC = 25C TA = 25C TA = 25C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 30 20 19 15 2.5 14.5 11 1.43 117 91 93.75 230 45 -- 55 to 175 78 6.0 450 W A A C A V/ns mJ W A W A Unit V V A
G S
N-Channel
4 4 12 1
3
CASE 369AA DPAK (Bent Lead) STYLE 2
2 3 CASE 369AD CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK)
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain YWW 48 04NG 4 Drain YWW 48 04NG
4 Drain
Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain--to--Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 30 A, RG = 25 ) Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
TL
260
C
2 1 23 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4804N G = Year = Work Week = Device Code = Pb--Free Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2010
June, 2010 - Rev. 6 -
1
Publication Order Number: NTD4804N/D
YWW 48 04NG
NTD4804N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Junction--to--Case (Drain) Junction--to--TAB (Drain) Junction--to--Ambient -- Steady State (Note 1) Junction--to--Ambient -- Steady State (Note 2) 1. Surface--mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface--mounted on FR4 board using the minimum recommended pad size. Symbol RJC RJC--TAB RJA RJA Value 1.6 3.5 60 105 Unit C/W
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Parameter OFF CHARACTERISTICS Drain--to--Source Breakdown Voltage Drain--to--Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) VGS = 10 to 11.5 V VGS = 4.5 V Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate--to--Source Charge Gate--to--Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time td(on) tr td(off) tf td(on) tr td(off) tf VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 18 20 24 8 10 19 35 5 ns ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 11.5 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A 4490 VGS = 0 V, f = 1.0 MHz, VDS = 12 V 952 556 30 5.5 13 13 73 nC 40 nC pF gFS ID = 30 A ID = 15 A ID = 30 A ID = 15 A VDS = 15 V, ID = 15 A VGS = 0 V, VDS = 24 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 30 26 1.0 10 100 1.5 7.6 3.4 3.4 4.7 4.6 23 S 5.5 4.0 2.5 nA V mV/C mA Symbol Test Condition Min Typ Max Unit
Gate--to--Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain--to--Source On Resistance
VDS = 0 V, VGS = 20 V VGS = VDS, ID = 250 mA
V mV/C m
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures.
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NTD4804N
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Parameter DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD tRR ta tb QRR LS LD LD LG RG TA = 25C VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.81 0.72 34 19 15 30 nC ns 1.2 V Symbol Test Condition Min Typ Max Unit
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance Drain Inductance, DPAK Drain Inductance, IPAK Gate Inductance Gate Resistance
2.49 0.0164 1.88 3.46 0.6
nH
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3
NTD4804N
TYPICAL PERFORMANCE CURVES
240 ID, DRAIN CURRENT (AMPS) 200 160 120 80 40 0 4V 240 ID, DRAIN CURRENT (AMPS) 200 160 120 80 40 0
10 V 6V
TJ = 25C 4.5 V
VDS 10 V
3.6 V 3.2 V 0 1 2 3 4 5
TJ = 125C TJ = 25C TJ = --55C 0 1 2 3 4 5 6 7 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN--TO--SOURCE RESISTANCE () 0.010 0.009 0.008 0.007 0.006 0.005 0.004 0.003 2 4 6 8 ID = 30 A TJ = 25C RDS(on), DRAIN--TO--SOURCE RESISTANCE () 0.01
Figure 2. Transfer Characteristics
TJ = 25C
0.0075 VGS = 4.5 V 0.005 VGS = 11.5 V
0.0025
10
0 10
20
30
40
50
60
70
80
90 100
VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate- -Source -toVoltage
RDS(on), DRAIN--TO--SOURCE RESISTANCE (NORMALIZED) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 --50 --25 0 25 50 75 100 125 150 175 100 0 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) 10,000 100,000
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V TJ = 175C
1000
TJ = 125C
5
10
15
20
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain- -Source Leakage Current -tovs. Drain Voltage
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NTD4804N
TYPICAL PERFORMANCE CURVES
6000 Ciss 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 15 VDS = 0 V 10 VGS = 0 V 10 15 20 Crss Coss Crss 25 30 0 5 5 VGS VDS 5 QT 4 3 2 1 0 Q1 Q2
TJ = 25C
Ciss
VGS , GATE--TO--SOURCE VOLTAGE (VOLTS)
ID = 30 A TJ = 25C 0 5 10 20 15 25 QG, TOTAL GATE CHARGE (nC) 30
GATE--TO--SOURCE OR DRAIN--TO--SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000 30 IS, SOURCE CURRENT (AMPS)
Figure 8. Gate- -Source and Drain- -Source -To-ToVoltage vs. Total Charge
VDD = 15 V ID = 30 A VGS = 11.5 V tr td(off) tf
VGS = 0 V 25 20 15 10 5 0 0 TJ = 25C
t, TIME (ns)
100
10
td(on)
1
1
10 RG, GATE RESISTANCE (OHMS)
100
0.2
0.4
0.6
0.8
1.0
VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN--TO--SOURCE AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) 500
Figure 10. Diode Forward Voltage vs. Current
ID = 30 A 400 300 200 100 0 25
10 ms 100 100 ms VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 ms 10 ms dc 100
10
1
10 1 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C)
175
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
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NTD4804N
TYPICAL PERFORMANCE CURVES
100 I D, DRAIN CURRENT (AMPS) 125C 100C 25C
10
1
1
100 10 PULSE WIDTH (ms)
1000
Figure 13. Avalanche Characteristics
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.0
D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE t1
0.1
P(pk)
t2 DUTY CYCLE, D = t1/t2 1.0E--03 1.0E--02 t, TIME (ms)
RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) -- TC = P(pk) RJC(t)
0.01 1.0E--05
1.0E--04
1.0E--01
1.0E+00
1.0E+01
Figure 14. Thermal Response
ORDERING INFORMATION
Order Number NTD4804NT4G NTD4804N--1G NTD4804N--35G Package DPAK (Pb--Free) IPAK (Pb--Free) IPAK Trimmed Lead (3.5 0.15 mm) (Pb--Free) Shipping 2500/Tape & Reel 75 Units/Rail 75 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NTD4804N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE) CASE 369AA--01 ISSUE B
C A B c2
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 ------ 0.040 0.155 -----MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 -----1.01 3.93 ------
E b3 L3
1 4
A
D
2 3
Z
DETAIL A
H
L4
b2 e
b 0.005 (0.13)
M
c C L2
GAUGE PLANE
H C L L1 DETAIL A
SEATING PLANE
A1
ROTATED 90 CW
SOLDERING FOOTPRINT*
6.20 0.244 3.00 0.118
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
2.58 0.102
5.80 0.228
1.60 0.063
6.17 0.243
SCALE 3:1
mm inches
*For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NTD4804N
PACKAGE DIMENSIONS
3.5 MM IPAK, STRAIGHT LEAD CASE 369AD--01 ISSUE O
E L2 E3 A A1 E2
L1
D L b1
2X
D2
NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 -----6.35 6.73 4.70 -----4.45 5.46 2.28 BSC 3.40 3.60 -----2.10 0.89 1.27
T
SEATING PLANE
A1 A2
3X
e b 0.13
M
E2 D2
T
OPTIONAL CONSTRUCTION
IPAK (STRAIGHT LEAD DPAK) CASE 369D--01 ISSUE B
B V R
4
C E Z
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 -----MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ------
S --TSEATING PLANE
A
1 2 3
K
F D G
3 PL
J
H
M
0.13 (0.005)
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTD4804N/D

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